The present invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method and, in particular, to a so-called dual bit EEPROM memory cell.
As an alternative to conventional mechanical storage devices, recently nonvolatile semiconductor memory devices having nonvolatile semiconductor memory cells such as, for example, FLASH, EPROM, EEPROM, FPGA memory cells and the like have gained greater and greater acceptance. Such rewritable nonvolatile semiconductor memory cells can store data over a long period of time and without the use of a voltage supply.
Such semiconductor memory cells usually comprise a semiconductor substrate, an insulating tunnel layer, a storage layer, an insulating dielectric layer and a conductive control layer. In order to store information, charges are introduced into the charge-storing layer from a semiconductor substrate. Examples of methods for introducing the charges into the storage layer are injection of hot charge carriers and Fowler-Nordheim tunnelling.
In particular, an information content per unit area, the charge retention properties and the operating voltages for reading and programming are of importance in the realization of such nonvolatile semiconductor memory cells. In order to improve a charge retention time, in this case use has increasingly been made in particular of nonvolatile semiconductor memory cells with electrically non-conductive charge storage layers, as a result of which, even in the case of partly inadequate insulation layers, a leakage current can be prevented and the charge retention properties can thus be improved.
Furthermore, so-called multibit semiconductor memory cells have been developed, which can realize a multiplicity of information contents or bits in a memory cell. The information content per unit area has been able to be significantly improved in this way.
The present invention relates, in particular, to a dual bit semiconductor memory cell with which two bits can be stored in nonvolatile fashion.
Such a dual bit semiconductor memory cell is known for example from the document U.S. Pat. No. 6,011,725 and is described below by means of FIG. 1.
In accordance with FIG. 1, such a two-bit EEPROM memory cell has a semiconductor substrate 1, which is p-doped, for example, and which has an n+-doped source region 7 and drain region 8 with associated terminals source and drain terminals S and D. It should be pointed out that a symmetrical construction is used in such a cell, for which reason the terms source and drain are not necessarily meaningful. In actual fact, the source region 7, for example, can also be connected as the drain region and the drain region 8 can also be connected as the source region.
In accordance with FIG. 1, the source and drain regions 7 and 8 define a channel region lying in between. A first insulation layer 2, an electrically non-conductive charge storage layer 3, a second insulation layer 4 and an electrically conductive control layer 10, which has a gate terminal G, are situated at the surface of said channel region. In accordance with FIG. 1, silicon nitride is used as the electrically non-conductive charge storage layer 3. For the programming, i.e. writing and erasing of this conventional nonvolatile semiconductor memory cell, an injection of hot charge carriers is essentially carried out, in which case, for writing, for example hot electrons are injected into the charge storage layer 3 on the drain side and, for erasing, hot holes are injected on the drain side. Since a symmetrical dual bit memory cell is involved, it is also possible, in the same way, for charge carriers to be injected into the charge storage layer 3 on the source side, in which case, however, the source region 7 is connected as the drain. With regard to the method for reading from, writing to and erasing such a memory cell, reference is explicitly made to the document U.S. Pat. No. 6,011,725.
Although extraordinarily high charge retention properties are already obtained at relatively low programming voltages in the case of such a conventional semiconductor memory cell, disadvantages have nonetheless been found which are of importance in particular in the case of a multiple programming over a long period of time. This is due in particular to the fact that the hot holes required for erasing are generally generated by means of an avalanche effect in the field of the p-n diode and therefore do not fall exactly at the same place in the charge storage layer 3 as the hot electrons introduced in the course of writing. For a memory location RB (right bit) arranged on the right, in the same way as for a left memory location LB (left bit) arranged on the source side, the problem arises that the electrons and holes are not introduced exactly at the same place and, consequently, a slight charge shift takes place. This imprecise compensation generally leads to threshold value shifts in the memory cell and thus to read current changes. This in turn causes an increased inaccuracy in an evaluation circuit (not illustrated).
A further point whereby the charge retention properties of this conventional semiconductor memory cell are adversely affected is caused by the fact that even though the charge storage layer 3 is electrically non-conductive, a small charge movement nevertheless takes place. This charge movement within the charge storage layer 3 is primarily based on drift and diffusion processes which lead to a slow redistribution of the charges in the charge storage layer 3. The illustration in accordance with FIG. 1 shows, by way of example, a solid charge distribution curve V, as results shortly after the writing of electrons, for example, at the local memory locations LB and RB. This distribution V changes, however, on account of drift and diffusion processes, the broadened distribution curve V′ illustrated by a broken line being established in the charge storage layer 3 after a predetermined time has elapsed. However, the charge density stored in the local memory locations LB and RB is reduced as a result. The redistribution of the charges within the charge storage layer 3 alters the threshold voltage of the semiconductor memory cell, which in turn leads to a loss of information or at least to increased requirements in the evaluation circuit (not illustrated).